Bachelor thesis · ETH Zurich, SPCL · 2025
HBDIA: Hybrid Blocked-DIA
Sparse matrices from stencils have strong diagonal structure, but real matrices also contain irregular outliers. HBDIA cuts the matrix into warp-wide column blocks, keeps locally dense diagonals in a blocked DIA layout for coalesced GPU access, and relegates sparse diagonals to a COO part that the Grace CPU of an NVIDIA GH200 can process concurrently. A performance model of transfer and aggregation costs guides the split. Advisors: Prof. Dr. Torsten Hoefler and Yakup Koray Budanaz.
Hover an entry to see where it lands. Columns are cut into blocks of 8; a diagonal with enough entries in a block goes to the GPU, the rest to the CPU.
My contribution
- Designed the HBDIA format and a direct two-pass COO → HBDIA conversion.
- Implemented the SpMV GPU kernel with fully coalesced block access, CPU COO fallback and multi-GPU execution via MPI.
- Developed a performance model for heterogeneous CPU–GPU execution on tightly coupled systems.
Results
- Up to 2.2× faster than cuSPARSE on stencil matrices.
- Up to 1.6× on a PDE-constrained optimisation matrix (nlpkkt240) and 1.5× on a 3D fluid channel simulation.
- Storage stays below COO even with up to 100% added random entries.